#ifndef CPUDATAWIDTH
  #define CPUDATAWIDTH 64	//64-bit
#endif
////SFR
#define	a_debugport	0x00000000
#define	a_intrctrl	0x00000004
#define	a_intren	0x00000008 //Interrupt Enable, b0~b7 for trap 0x10~0x17
#define	a_intrenb	0x00000009 //Interrupt global Enable, b0=0 enable interrupt, on reset or interrupt set b0=1, reti set b0=0
#define	a_intrpriority	0x0000000C //Interrupt Priority,1=high,0=low,b0~7 for trap 0x10~0x17
#define	a_TC0		0x00000010 //Read only=1ms clock counter=100000 for 100MHz
#define	a_TC1		0x00000014 
#define	a_TC2		0x00000018
#define	a_T0		0x00000020 //Increase every clock, Interrupt 0x10 when T0=TC0 then rewind to 0
#define	a_T1		0x00000024 //Increase every 1ms, Interrupt 0x11 when T1=TC1, no rewind
#define	a_T2		0x00000028 //Decrease every clock, Interrupt 0x12 when T2=0 then reload from TC2
#define	a_Key		0x00000030 //Interrupt 0x13=Key input
#define	a_IRA		0x00000034 //Interrupt return address
#define	a_BRA		0x00000038 //32bit general register
#define	a_PBANK		0x0000003C //Predict flag bank
#define	a_PRED0		0x00000040 //Predict flag set 0
#define	a_PRED1		0x00000041 //Predict flag set 1
#define	a_PRED2		0x00000042 //Predict flag set 2
#define	a_PRED3		0x00000043 //Predict flag set 3
#define	a_PRED4		0x00000044 //Predict flag set 4
#define	a_PRED5		0x00000045 //Predict flag set 5
#define	a_PRED6		0x00000046 //Predict flag set 6
#define	a_PRED7		0x00000047 //Predict flag set 7
#define	a_PRED8		0x00000048 //Predict flag set 8
#define	a_PRED9		0x00000049 //Predict flag set 9
#define	a_PRED10	0x0000004A //Predict flag set 10
#define	a_PRED11	0x0000004B //Predict flag set 11
#define	a_PRED12	0x0000004C //Predict flag set 12
#define	a_PRED13	0x0000004D //Predict flag set 13
#define	a_PRED14	0x0000004E //Predict flag set 14
#define	a_PRED15	0x0000004F //Predict flag set 15
//Byte of intrctrl
#define	a_INTR_ENA	0x00000004	//byte
#define	b_INTR_ENA	0x01		//b0=0:disable interrupt
#define a_TimerCtrl	0x00000006
#define b_T0_start	0x01	//start T0
#define b_T1_start	0x02	//start T1
#define b_T2_start	0x04	//start T2

#define	STI	store.1		R0,R0,a_intrenb	
#define	stop	trap	0xFFFF	;//suspend
#define ret	jmp.reg R31